Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 529
UG586 November 30, 2016
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
If the design has multiple controllers, the controller options page is repeated for each of the
controllers. This page is partitioned into a maximum of nine sections. The number of
partitions depends on the type of memory selected. The controller options page also
contains these pull-down menus to modify different features of the design:
• Frequency – This feature indicates the operating frequency for all the controllers. The
frequency block is limited by factors such as the selected FPGA and device speed grade.
• PHY to Controller Clock Ratio – This feature determines the ratio of the physical layer
(memory) clock frequency to the controller and user interface clock frequency. The user
interface data bus width of the 2:1 ratio is four times the width of the physical memory
interface width.
• Memory Type – This feature selects the type of memory parts used in the design.
• Memory Part – This option selects a memory part for the design. Selections can be
made from the list or a new part can be created.
• Data Width – The data width value can be selected here based on the memory type
selected earlier. The list shows all supported data widths for the selected part. One of
the data widths can be selected.
• Data Mask – This option allocates data mask pins when selected. This option should be
deselected to deallocate data mask pins and increase pin efficiency. This option is
disabled for memory parts that do not support data mask.
X-Ref Target - Figure 4-17
Figure 4-17: Controller Options Page
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