Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 610
UG586 November 30, 2016
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
mc_cs_n
[CS_WIDTH ×
nCS_PER_RANK ×
nCK_PER_CLK – 1:0]
Input –
mc_cs_n [CS_WIDTH – 1:0] is the cs_n
associated with the first command in the
sequence.
mc_cke [nCK_PER_CLK – 1:0] Input –
mc_cke [nCK_PER_CLK – 1:0] is the CKE
associated with the DRAM interface. This
signal is valid when the CKE_ODT_AUX
parameter is set to FALSE.
mc_wrdata
[2 × nCK_PER_CLK ×
DQ_WIDTH – 1:0]
Input –
This is the write data to the dedicated PHY.
It is 4x the memory DQ width.
mc_wrdata_mask
[2 × nCK_PER_CLK ×
(DQ_WIDTH/8) – 1:0]
Input –
This is the write data mask to the dedicated
PHY. It is 4x the memory DM width.
mc_wrdata_en 1 Input
Active-
High
This signal is the WREN input to the DQ
OUT_FIFO.
mc_cmd_wren 1 Input
Active-
High
This signal is the write enable input of the
address/command OUT_FIFOs.
mc_ctl_wren 1 Input
Active-
High
This signal is the write enable input to the
PHY control word FIFO in the dedicated
PHY block.
mc_cmd [2:0] Input –
This signal is used for PHY_Ctl_Wd
configuration:
0x04: Non-data command (No column
command in the sequence of commands)
0x01: Write command
0x03: Read command
mc_data_offset [5:0] Input –
This signal is used for PHY_Ctl_Wd
configuration:
0x00: Non-data command (No column
command in the sequence of commands)
CWL + COL cmd position: Write command
0x00: Read command
mc_aux_out0 [3:0] Input
Active-
High
This is the auxiliary outputs field in the PHY
control word used to control ODT and CKE
assertion.
mc_aux_out1 [3:0] Input
Active-
High
This is the auxiliary outputs field in the PHY
control word used to control ODT and CKE
assertion for four-rank interfaces.
mc_rank_cnt [1:0] Input –
This is the rank accessed by the command
sequence in the PHY control word.
phy_mc_ctl_full 1 Output
Active-
High
Bitwise AND of all the Almost FULL flags of
all the PHY Control FIFOs. The Almost FULL
flag is asserted when the FIFO is one entry
away from being FULL.
Table 4-24: Memory Controller to Calibration Logic Interface Signals (Cont’d)
Signal Name Width
I/O
To/From
PHY
Type Description
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