Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 628
UG586 November 30, 2016
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Chapter 4: LPDDR2 SDRAM Memory Interface Solution
DATA_CTL_B0,
DATA_CTL_B1,
DATA_CTL_B2
Defines mode of use of
byte lanes in a given I/O
bank. A 1 in a bit position
indicates a byte lane is
used for data, and a 0
indicates it is used for
address/control. This
parameter varies based on
the pinout and should not
be changed manually in
generated design.
4'b1100: With respect to the
BYTE_LANE example, two byte
lanes are used for Data and one for Address/Control.
PHY_0_BITLANES,
PHY_1_BITLANES,
PHY_2_BITLANES
12-bit parameter per byte
lane used to determine
which I/O locations are
used to generate the
necessary PHY structures.
This parameter is provided
as per bank. Except
CK/CK# pins, all Data and
Address/Control pins are
considered for this
parameter generation.
DQS pins are excluded
when used for DQS pins in
data byte groups. One of
the unused pins where
Data byte group is
allocated should be set to
1 which is used for
DQS0_MAP (DQS still
allocated to DQS I/O only
and extra bit is used
internally in the PHY). This
parameter varies based on
the pinout and should not
be changed manually in
generated design.
This parameter denotes for all byte groups of a selected bank.
All 12 bits are denoted for a byte lane. For example, this
parameter is 48'hFFE_FFF_000_ DF6 for one bank.
12'hDF6 (12'b1101_1111_0110): bit lines 0, 3, and 9 are not
used, the rest of the bits are used.
CK_BYTE_MAP
Bank and byte lane
location information for
the CK/CK#. An 8-bit
parameter is provided per
pair of signals.
•[7:4] – Bank position.
Values of 0, 1, or 2 are
supported
• [3:0] – Byte lane position
within a bank. Values of
0, 1, 2, and 3 are
supported.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
Upper-most Data or Address/Control byte group selected bank
is referred to as Bank 0 in parameters notation. Numbering of
banks is 0, 1, and 2 from top to bottom.
Byte groups T0, T1, T2, and T3 are numbered in parameters as
3, 2, 1 and 0, respectively.
144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_
03: This parameter is denoted for 18 clock pairs with 8 bits for
each clock pin. In this case, only one clock pair is used. Ordering
of parameters is from MSB to LSB (that is, CK[0]/ CK#[0]
corresponds to LSB 8 bits of the parameter).
8'h13: CK/CK# placed in bank 1, byte lane 3.
8'h20: CK/CK# placed in bank 2, byte lane 0.
Table 4-27: LPDDR2 SDRAM Memory Interface Solution Pinout Parameters (Cont’d)
Parameter Description Example