Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 630
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
MASK0_MAP
Bank and byte lane
position information for
the data mask. See the
ADDR_MAP description.
This parameter varies
based on the pinout and
should not be changed
manually in generated
design.
See the ADDR_MAP example.
DQS0_MAP
Bank and byte lane
position information for
the DQS of respective
data lanes.
This parameter
varies based on the pinout
and should not be
changed manually in
generated design.
See the DQS_MAP example.
ADDR_0_BITLANES,
ADDR_1_BITLANES,
ADDR_2_BITLANES
12-bit parameter per
byte lane used to
determine which I/O
locations are used to
generate the necessary
PHY structures. This
parameter is provided as
per bank where
Address/Control are
selected. Except CK/CK#
and Data pins, only the
Address/Control pins are
considered for this
parameter generation.
DQS pins are excluded
when used for CK/CK# in
command/address byte
group.
This parameter
varies based on the pinout
and should not be
changed manually in
generated design.
See the PHY_0_BIT_LANES example.
Table 4-27: LPDDR2 SDRAM Memory Interface Solution Pinout Parameters (Cont’d)
Parameter Description Example
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English