Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 129
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
When the wr_bytes command is given, the Memory Controller performs a
read-modify-write (RMW) cycle. When a wr_bytes command is at the head of the queue,
it first issues a read. But unlike a normal read command, the request remains in the queue.
A bit is set in the read response queue indicating this is a RMW cycle. When the read data
is returned for this read command, app_rd_data_valid is not asserted. Instead, the ECC
is decoded, corrections if any are made, and the data is written into the ECC data buffer.
Meanwhile, the original wr_bytes command is examining all read returns. Based on the
data_buf_addr stored in the read return queue, the wr_bytes request can determine
when its read data is available in the ECC data buffer. Now, the wr_bytes request starts
arbitrating to send the write command. When the command is granted, data is fetched from
the write data buffer and the ECC data buffer, merged as directed by the byte enables, ECC
is computed, and data is written to the DRAM. The wr_bytes command has significantly
lower performance than normal write commands.
In the best case, each wr_bytes command requires a DRAM read cycle and a DRAM write
cycle instead of simple DRAM write cycle. Read-to-write and write-to-read turnaround
penalties further degrade throughput.
The Memory Controller can buffer up to nBANK_MACHS wr_bytes commands. As long as
these commands do not conflict on a rank-bank, the Memory Controller strings together
the reads and then the writes, avoiding much of the read-to-write and write-to-read
turnaround penalties. However, if the stream of wr_bytes commands is to a single
rank-bank, each RMW cycle is completely serialized and throughput is significantly
degraded.
IMPORTANT: If performance is important, it is best to avoid the wr_bytes command.
Table 1-56 provides the details of ECC ports at the user interface.
Table 1-56: User Interface for ECC Operation
Signal Direction Description
app_correct_en_i Input
When asserted, this active-High signal corrects single
bit data errors. This input is valid only when ECC mode
is enabled.
app_ecc_multiple_err[7:0] Output
This signal is applicable when ECC is enabled. It is
valid along with app_rd_data_valid. The
app_ecc_multiple_err signal is non-zero if the read
data from the external memory has two bit errors per
beat of the read burst. The SECDED algorithm does
not correct the corresponding read data and puts a
non-zero value on this signal to notify the corrupted
read data at the UI.
This signal is four bits wide in 2:1 mode.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English