Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 2
UG586 November 30, 2016
www.xilinx.com
Date Version Revision
11/30/2016 4.1
• Renamed QuestaSim to Questa Advanced Simulator.
QDR II+
• Updated qdr_k_n/p directions in Physical Interface Signals table.
• Updated in qdr_k_n/p directions I/O Standards table.
RLDRAM II/RLDRAM 3
• Updated rld_dk_p/n directions in Physical Interface Signals table.
• Updated rld_dk_p/n directions in RLDRAM II I/O Standards and RLDRAM 3 Standards
tables.
10/05/2016 4.1
• Updated to core version 4.1.
• Updated file name path to _ex/imports in all sections.
DDR3 and DDR2
• Updated Controller Options Page figure.
• Added Number of Bank Machines bullet in the Controller Options section.
06/08/2016 4.0
DDR3 and DDR2
• Updated Memory Part description in Controller Option section.
• Added app_ecc_single_err[7:0] in Table 1-17: User Interface table.
• Added app_ecc_single_err[7:0] and note in Table 1-56: User Interface for ECC
Operation.
• Updated description in dbg_pi_phase_locked_phy4lanes and
dbg_pi_dqs_found_lanes_phy4lanes in Table 1-74: DDR2/DDR3 Debug Signals.
04/06/2016 3.0
• Updated to core version 3.0.
• Updated Termination for all sections.
• Updated 1.0 µF capacitor in General Memory Routing Guideline chapter.
DDR3 and DDR2
• Added note in FPGA Options section.
• Added note in Interfacing to the Core section.
• Updated sys_rst descriptions in DDR3 and DD2 Configuration sections.
• Added note in Debug Signals section.
• Updated reset description in General Checks section.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English