Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 3
UG586 November 30, 2016
www.xilinx.com
11/18/2015 2.4
• Added asynchronous to sys_rst in all sections.
• Added note to RELAXED mode in DDR3/DDR2 and LDDR2 sections.
• Updated code in all Configuration sections
• Added Important jitter note in Pinout Requirements in all sections.
DDR3 and DDR2
• Added Synplify Pro Black Box Testing section.
QDR II+
• Updated DEBUG_PORT Signal Descriptions, Write Init Debug Signal Map, and Read
Stage 1 Debug Signal Map tables.
• Updated Calibration of Read Clock and Data description.
• Updated Write Calibration description.
RLDRAM II/ RLDRAM 3
• Updated Read Stage 1 Debug Signal Map table.
• Updated Calibration of Read Clock and Data description.
09/30/2015 2.4
• Added CLOCK_DEDICATED_ROUTE Constraints in all sections.
DDR3 and DDR2
• Updated Trace Lengths section.
QDR II+
• Added Termination section.
RLDRAM II/ RLDRAM 3
• Added Termination section.
• Updated Margin Check section.
• Updated Automatic Margin Check section.
• Updated Table 3-33: Debug Port Signals.
LPDDR2
• Updated Trace Lengths section.
Appendix
• Added General Memory Routing Guidelines.
06/24/2015 2.3
• Added Simulation Flow Using VCS and IES to all sections.
• Added Clocking sections to QDR II+, RLDRAM II/RLDRAM 3, and LPDDR2 chapters.
RLDRAM II/ RLDRAM 3
• Added address/control signal and SSI descriptions in Pinout Requirements section.
• Updated Input Clock Guidelines section.
Date Version Revision
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English