Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 4
UG586 November 30, 2016
www.xilinx.com
04/01/2015 2.3
• Updated description in all Configuration sections.
• Updated SIM_BYPASS_INIT_CAL.
Chapter 1
• Added description in Setting DDR3 Memory Parameter Option section.
• Added Note to Answer Record: 54025 in Controller Options section.
• Added description to app_rd_data_end in Table 1-17: User Interface.
• Updated Table 1-19: AXI4 Slave Interface Parameters.
• Updated description in AXI4 Slave Interface Signals section.
• Updated Time Division Multiplexing (TDM), Round-Robin, and Read Priority
(RD_PRI_REG) sections.
• Updated GES description in Calibration Times section.
• Updated Fig. 1-50: Clocking Architecture.
• Updated Table 1-87: Memory Controller to Calibration Logic Interface Signals.
• Updated AXI Addressing section.
• Updated Write Path section.
• Updated Fig. 1-84: Command Processing.
• Updated Physical Layer Interface (Non-Memory Controller Design) section.
• Updated CK signal description in Trace Length section.
• Updated Fig. 1-93: Calibration Stages.
• Updated description in Determine the Failing Calibration Stage section.
• Updated Table 1-100: DDR2/DDR3 Debug Signals.
• Updated Table 1-102: Debug Signals of Interest for Write Leveling Calibration.
• Updated Table 1-103: Debug Signals of Interest for MPR Read Leveling Calibration.
• Updated calibration overview in Debugging OCLKDELAYED Calibration Failures
section.
• Updated Debug bullets in Debugging OCLKDELAYED Calibration Failures section.
• Updated Table 1-104: Debug Signals of Interest for OCLKDELAYED Calibration to
Table 1-106: Debug Signals of Interest for Read Leveling Stage 1 Calibration.
• Updated Table 1-108: Calibration Time in Hardware.
• Updated Checking and Varying Read Timing to Manual Window Check sections.
• Updated Calibration Times section.
Chapter 2
• Updated Fig. 2-43: High-Level PHY Block Diagram for a 36-Bit QDR II+ Interface.
• Updated Margin Check and Automated Margin Check sections.
Continued
Chapter 3
• Updated description in Interfacing with the Core through the Client Interface section.
Chapter 4
• Corrected app_wdf_data[APP_DATA_WIDTH – 1:0] and
app_wdf_mask[APP_MASK_WIDTH – 1:0] sections.
• Updated Fig. 4-43: Clocking Architecture.
• Updated Read Path section.
Date Version Revision
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English