Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 339
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Table 2-13 contains parameters set up by the MIG tool based on the pinout selected. When
making pinout changes, Xilinx recommends rerunning the MIG tool to set up the
parameters properly. See Pinout Requirements, page 344. Mistakes to the pinout
parameters can result in non-functional simulation, an unroutable design, and/or trouble
meeting timing. These parameters are used to set up the PHY and route all the necessary
signals to and from it. The parameters are calculated based on Data Write, Data Read, and
Address/Control byte groups selected. These parameters do not consider the System
Signals selection (that is, system clock, reference clock, and status signals).
DEBUG_PORT
Turning on the debug port allows for use with the VIO of the
Vivado logic analyzer feature. This allows you to change the
tap settings within the PHY based on those selected though
the VIO. This parameter is always set to OFF in the
sim_tb_top module of the sim folder, because debug
mode is not required for functional simulation.
ON, OFF
Notes:
1. This parameter is prefixed with the module name entered in MIG during design generation. If the design is generated with
the module name as mig_7series_0, then IODELAY_GRP parameter name is mig_7series_0_IODELAY_MIG.
Table 2-12: 7 Series FPGAs QDR II+ SRAM Memory Interface Solution Configurable Parameters (Cont’d)
Parameter Description Options
Table 2-13: QDR II+ SRAM Memory Interface Solution Pinout Parameters
Parameter Description Example
BYTE_LANES_B0,
BYTE_LANES_B1,
BYTE_LANES_B2
Defines the byte lanes being used
in a given I/O bank. A 1 in a bit
position indicates a byte lane is
used, and a 0 indicates unused. This
parameter varies based on the
pinout and should not be changed
manually in generated design.
Ordering of bits from MSB to LSB is T0, T1, T2,
and T3 byte groups.
4'b1101: For a given bank, three byte lanes are
used, and one byte lane is not used.
CPT_CLK_SEL_B0,
CPT_CLK_SEL_B1,
CPT_CLK_SEL_B2
Three fields, one per possible I/O
bank. Defines which read capture
clocks are used for each byte lane
in given bank. MRCC read capture
clocks are placed in byte lanes 1
and/or 2, where parameter is
defined for each data byte lane to
indicate which read clock to use for
the capture clock. 8 bits per byte
lane, defined such that:
• [7:4] – 0 (bank below), 1 (current
bank), 2 (bank above) to indicate
in which bank the clock is placed.
• [3:0] – 1, 2 to indicate which of
two capture clock sources
This parameter varies based on the
pinout and should not be changed
manually in generated design.
32'h11_11_11_11 = Four data byte lanes, all using
the clocks in the same bank.
32'h11_11_01_01 = Four data byte lanes, two
lanes using the capture clock from the bank
below (16'h01_01), two using the capture clock
from the current bank (16'h11_11).
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English