Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 461
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Table 3-15 contains parameters set up by the MIG tool based on the pinout selected. When
making pinout changes, Xilinx recommends rerunning the MIG tool so the parameters are
set up properly; otherwise see Pinout Requirements, page 467. Mistakes to the pinout
parameters can result in non-functional simulation, an unroutable design, and/or trouble
meeting timing. These parameters are used to set up the PHY and route all the necessary
signals to and from it. The parameters are calculated based on Data and Address/Control
byte groups selected. These parameters do not consider the System Signals selection (that
is, system clock, reference clock, and status signals).
SIM_BYPASS_INIT_CAL
This simulation-only parameter is used to speed up
simulations, by skipping the initialization wait time and
speeding up calibration. SKIP_AND_WRCAL and
FAST_AND_WRCAL are options to SKIP or perform FAST
read calibration, but to simulate write calibration.
FAST, NONE,
SKIP_AND_WRCAL,
FAST_AND_WRCAL
SIMULATION
Set to “TRUE” for simulation; set to “FALSE” for
implementation.
“TRUE,” “FALSE”
DEBUG_PORT
Turning on the debug port allows for use with the VIO of
the Vivado logic analyzer feature. This allows you to
change the tap settings within the PHY based on those
selected though the VIO. This parameter is always set to
OFF in the sim_tb_top module of the sim folder, because
debug mode is not required for functional simulation.
ON, OFF
N_DATA_LANES
Calculated number of data byte lanes, used to set up signal
widths for using the debug port. This parameter should
not be changed.
DATA_WIDTH/9
DIFF_TERM_SYSCLK Differential Termination for System clock input pins “TRUE,” “FALSE”
DIFF_TERM_REFCLK
Differential Termination for IDELAY reference clock input
pins
“TRUE,” “FALSE”
nCK_PER_CLK
Number of memory clocks per FPGA logic clocks. This
parameter should not be changed.
RLDRAM II: 2
RLDRAM 3: 4
TCQ Register delay for simulation. 100
Notes:
1. This parameter is prefixed with the module name entered in MIG during design generation. If the design is generated with
the module name as mig_7series_0, then IODELAY_GRP parameter name is mig_7series_0_IODELAY_MIG.
Table 3-14: RLDRAM II Memory Interface Solution Configurable Parameters (Cont’d)
Parameter Description Options
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English