2 Parameters
2.2 List of parameters
SINAMICS G130/G150
432 List Manual (LH2), 04/2014, A5E03263479A
Dependency: If bit 2 is set from 1 to 0, p1811 = 0 is set.
Notice: Bit 1 = 0 can only be set under a pulse inhibit and for r0192.14 = 1.
Bit 2 can only be set to 1 subject to the following prerequisites:
- Pulse inhibit
- r0192.16 = 1
- p1800 < 2 x 1000/p0115[0]
Bit 12 can only be changed subject to the following prerequisites:
- preconditions, the same as bit 2 = 1
- p1810.3 = 0
For fast current changes, bit 15 = 1 together with p1802 = 0, 2 and p1803 > 106 % result in a significant increase in
the torque ripple. As a consequence, increasing the modulation limit must be checked on an application for
application basis.
Note: Re bit 00 = 0:
Voltage limitation from the minimum of the DC link voltage (lower ripple in the output current, reduced output
voltage).
Re bit 00 = 1:
Voltage limitation from averaged DC link voltage (higher output voltage with increased ripple in the output current).
The selection is only valid if the DC link compensation is not performed in the Control Unit (bit 1 = 0).
Re bit 01 = 0:
DC link voltage compensation in the modulator.
Re bit 01 = 1:
DC link voltage compensation in the current control.
Re bit 02 = 0:
A gating unit that does not permit wobbulation is used.
Edge modulation is not possible for a parallel connection with a single-winding system (p7003 = 0).
Bit 02 cannot be set to 0 if bit 12 = 1.
Re bit 02 = 1:
A gating unit that permits wobbulation is used.
For a wobbulation amplitude p1811 = 0, the maximum possible pulse frequency in p1800 = 2 x 1000 / p0115[0].
For a wobbulation amplitude p1811 > 0, the maximum possible pulse frequency in p1800 = 1000 / p0115[0].
If optimized pulse patterns has been activated (p1802 > 6), then a parameter save is required and switch-off and
switch-on again. This is displayed using a fault message (F01040).
Re bit 03 = 1:
The actual current value sensing and the determination of the valve ON times takes place with a double current
controller clock cycle and phase offset.
The activation is only possible with r0192.23 = 1 and p1810.12 = 0 - and takes effect the next time the system is
powered up.
Re bit 08 = 1:
Above the frequency threshold r1836[0], the pulse frequency is switched to the value in p1800. Below r1836[0]
(minus the hysteresis), the pulse frequency is reduced to the next possible pulse frequency (see r0114).
Re bit 09 = 1:
Above the frequency threshold r1836[1], the pulse frequency is increased to the next possible value. Below r1836[1]
(minus the hysteresis), the pulse frequency is reduced to the next possible pulse frequency.
If bit 8 is set to 0, bit 9 is automatically reset.
Re bit 10 = 0:
Pulse-locking function activated.
09 Pulse frequency reduction (speed
dependent) stage 2
Yes No -
10 Activate pulse-locking/pulse-dropping
function
Pulse-Dropping Pulse-Locking -
12 Pulse freq. can be asynchronously set to
curr. ctrl clock cycle
Yes No -
13 Pulse freq. reduction before optimized pulse
patterns for 500 µs
Yes No -
14 Deactivate maximum angular difference
adaptation
Yes No -
15 Increase overmodulation range Yes No -