5. The Internet Processor II ASIC on the SFM performs a route lookup for each packet
and decides how to forward it.
6. The Internet Processor II ASIC notifies the second Distributed Buffer Manager ASIC
(on the SFM) of the forwarding decision, and the Distributed Buffer Manager ASIC
forwards the notification to the FPC that hosts the appropriate outbound interface.
7. The I/O Manager ASIC on the FPC reassembles data cells stored in shared memory
into data packets as they are ready for transmission and passes them through the
Packet Director ASIC to the outbound PIC.
8. The outbound PIC transmits the data packets.
Related
Documentation
M40e Multiservice Edge Router Overview on page 15•
Data Flow Through the M120 Router Packet Forwarding Engine
Data flows through the M120 router Packet Forwarding Engine in this sequence:
1. Packets arrive at an incoming PIC interface.
2. The PIC passes the packets through the midplane to the FEB, where the I/O Manager
ASIC breaks them into 64-byte cells.
3. The Distributed Buffer Manager ASIC on the FEB distributes the data cells throughout
memory banks on the FEB.
4. The Internet Processor II ASIC on the FEB performs route lookups and makes
forwarding decisions.
5. The Internet Processor II ASIC notifies a second Distributed Buffer Manager ASIC on
the FEB, which forwards the notification to the outgoing interface.
6. The I/O Manager ASIC on the FEB reassembles data cells in shared memory into data
packets as they are ready for transmission and passes them to the outgoing PIC
through the midplane.
7. The outgoing PIC transmits the data packets.
Related
Documentation
M120 Multiservice Edge Router Overview on page 17•
Data Flow Through the M160 Router Packet Forwarding Engine
Data flows through the M160 router Packet Forwarding Engine in the sequence shown
in Figure 29 on page 129.
Copyright © 2012, Juniper Networks, Inc.128
M Series and T Series Routers Monitoring and Troubleshooting Guide
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